Document Preprocessing and Structuring Pipeline (Undergraduate Research at FIB)
Built an industrial-grade PDF-to-JSON pipeline using modular layout analysis and LLMs to structure complex Chinese technical documents with SOTA accuracy.
Portfolio
MIPS CPU Design & FPGA Acceleration (Coursework: Fundamental Experiment of Digital Logic and Processor)
Engineered a 5-stage pipelined MIPS CPU on FPGA to accelerate sparse matrix multiplication, validating hardware correctness through real-time visualization.
Probability Notes (Notes: Probability and Stochastic Process (I))
Authored a comprehensive technical manuscript for Probability and Stochastic Process (I), structuring concepts from measure theory to entropy with rigorous proofs and custom visualizations.
SBSPO: Self-Bootstrapping Alignment (Coursework: Deep Learning)
Proposed a supervision-free alignment framework for LLaVA 1.5 that utilizes a Reward Union strategy to reduce object hallucination by 81.2%, outperforming GPT-4V.
Secure Communication System Simulator (Coursework: Coding Theory)
Developed a full-link communication simulator integrating Viterbi decoding and custom encryption to optimize the trade-off between transmission security and image recovery quality.
Vehicle Comprehensive Management System (Coursework: Computer Program Design (II))
Engineered a C++/Qt6 client-server vehicle management system featuring O(log n) data retrieval, SHA-256 security, and cross-platform compatibility verified by GoogleTest.